1. Field of the Invention
The present invention relates to a protection circuit for use in protection of a MIS semiconductor device fabricated using a CMOS process from a semiconductor device from an excessively high voltage, and a semiconductor device including a protection circuit.
2. Description of the Related Art
Semiconductor devices fabricated with a CMOS process are generally less resistant to static electricity. In order to protect a semiconductor device from being damaged by static electricity, a protection circuit is typically provided at an external input-output terminal of the semiconductor device. A thyristor is widely used in such a protection circuit. A thyristor is a semiconductor device including two or more PN junctions. A fundamental structure of a thyristor is shown in FIG. 1.
FIG. 1 is a cross-sectional view showing a fundamental thyristor taken along a normal direction to a substrate surface. This fundamental thyristor includes a P-type silicon substrate 1. A low-concentration N-type semiconductor region 3 and a low-concentration P-type semiconductor region 4 are provided side by side in a horizontal direction on the silicon substrate 1. A high-concentration N-type semiconductor region 5 and a high-concentration P-type semiconductor region 7 are provided on the low-concentration N-type semiconductor region 3 and are separated by an isolation region 2. A high-concentration N-type semiconductor region 6 and a high-concentration P-type semiconductor region 8 are provided on the low-concentration P-type semiconductor region 4 and are separated by the isolation region 2. The isolation region 2 is also provided on an interface between the low-concentration N-type semiconductor region 3 and the low-concentration P-type semiconductor region 4 to separate the high-concentration P-type semiconductor region 7 and the high-concentration N-type semiconductor region 6 from each other.
Thus, the thyristor shown in FIG. 1 has a P-N-P-N structure. An anode terminal T1 is connected to the high-concentration N-type semiconductor region 5 and the high-concentration P-type semiconductor region 7, and a cathode terminal T2 is connected to the high-concentration N-type semiconductor region 6 and the high-concentration P-type semiconductor region 8. Note that the high-concentration P-type semiconductor region 7 and the high-concentration N-type semiconductor region 6 which are separated by the isolation region 2 are referred to as an anode and a cathode, respectively.
FIG. 2 is a graph showing the current-voltage characteristics of a typical thyristor where the voltage applied to the anode is changed while the cathode is set to be held at a reference potential (0 V). As shown in FIG. 2, the thyristor can allow a large amount of current to flow therethrough with an increase in voltage in the positive direction once it is switched ON. The thyristor can also allow a large amount of current to flow therethrough with an increase in voltage in the negative direction due to the forward direction characteristics of the PN junction. Therefore, thyristors are often used as static electricity protection circuits.
Note electrostatic discharge is caused by combining any two terminals having positive and negative polarities. Therefore, the static electricity protection circuit needs to be capable of allowing a sufficient amount of discharge current to flow between any two terminals.
A conventional protection circuit for such electrostatic discharge will be described with reference to FIG. 3. FIG. 3 is a block diagram showing a semiconductor device including a conventional static electricity protection circuit. In this semiconductor device, a protection circuit is connected to an external input-output terminal PAD. In the protection circuit, a P-type MOS transistor PMOS is provided between the external input-output terminal PAD and a power supply terminal VDD, and a resistance portion R1 and an N-type MOS transistor NMOS are provided between the P-type MOS transistor PMOS and a ground terminal VSS. A power supply line is represented by line a-b in FIG. 3, and a ground line is represented by line c-d in FIG. 3.
A first thyristor SCR1 is provided between the external input-output terminal PAD and the ground line c-d. The anode portion of the first thyristor SCR1 is connected to the external input-output terminal PAD, and the cathode portion is connected to the ground line c-d. A second thyristor SCR2 is provided between the power supply line a-b and the ground line c-d. The anode portion of the second thyristor SCR2 is connected to the power supply line a-b, and the cathode portion is connected to the ground line c-d.
An internal circuit 50 is connected via a resistance portion R2 to the external input-output terminal PAD. The internal circuit 50 is also connected to the power supply terminal VDD and the ground terminal VSS.
In the exemplary semiconductor device shown in FIG. 3, the P-type MOS transistor PMOS functions as an output transistor. If the P-type MOS transistor PMOS functions as an input transistor, typically, the gate thereof is connected to the internal circuit 50 side of the resistance portion R2.
The resistance value of the resistance portion R1 connected to the N-type MOS transistor NMOS is about 10xcexa9, which is similar to the resistance value of a typical resistance portion connected to an N-type MOS transistor. In the semiconductor device shown in FIG. 3, a connection node between the P-type MOS transistor PMOS and the N-type MOS transistor NMOS is connected via the resistance portion R2 to an input portion of the internal circuit 50. Alternatively, the internal circuit 50 may be connected via the resistance portion R2 between the resistance portion R1 and the N-type MOS transistor NMOS.
The resistance portion R2 connected to the input side of the internal circuit 50 is provided so as to protect the gate of the internal circuit 50, and has a resistance value of about 150xcexa9 to about 400xcexa9. If the external input-output terminal PAD is used as an input terminal of the internal circuit 50, the resistance portion R2 may be provided between the connection node between the P-type MOS transistor PMOS and the N-type MOS transistor NMOS, and the external input-output terminal PAD. If the external input-output terminal PAD is used as an output terminal of the internal circuit 50, an output current cannot be obtained and therefore the resistance portion R2 cannot be provided between the power supply terminal VDD and the external input-output terminal PAD.
As described above, a thyristor has a high capability of discharging currents in both positive and negative directions. Therefore, in the semiconductor device shown in FIG. 3, the second thyristor SCR2 functions as a protection element against electrostatic discharge conducted between the power supply terminal VDD and the ground terminal VSS, so that the semiconductor device exhibits a high level of static electricity endurance. The first thyristor SCR1 functions as a protection element against electrostatic discharge conducted between the external input-output terminal PAD and the ground terminal VSS, so that the semiconductor device exhibits a high level of static electricity endurance.
Next, electrostatic discharge conducted between the external input-output terminal PAD and the power supply terminal VDD will be described. FIG. 4 is a cross-sectional view showing a configuration of the P-type MOS transistor PMOS of the semiconductor device shown in FIG. 3. The P-type MOS transistor PMOS shown in FIG. 4 includes a P-type silicon substrate 9. A low-concentration N-type semiconductor region 10 is provided on the P-type silicon substrate 9. A gate polysilicon 14 is provided via a gate oxide film 40 on the low-concentration N-type semiconductor region 10. A high-concentration P-type semiconductor region 13 and a high-concentration P-type semiconductor region 12 are provided on the low-concentration N-type semiconductor region 10, interposing the gate polysilicon 14 and the gate oxide film 40. A high-concentration N-type semiconductor region 11 is provided to be adjacent the high-concentration P-type semiconductor region 12. The high-concentration P-type semiconductor region 13 is connected to the external input-output terminal PAD. The high-concentration P-type semiconductor region 12 and the high-concentration N-type semiconductor region 11 are connected to the power supply terminal VDD.
In the thus-constructed P-type MOS transistor PMOS, a parasitic diode is present at a junction between the high-concentration P-type semiconductor region 13 connected to the external input-output terminal PAD and the low-concentration N-type semiconductor region 10.
Since a parasitic diode is present in the P-type MOS transistor PMOS, a portion of the semiconductor device shown in FIG. 3 represented by path 1 (from the external input-output terminal PAD to the power supply terminal VDD via the P-type MOS transistor PMOS) has current-voltage characteristics as shown in FIG. 5 when the potential of the power supply terminal VDD is changed where the external input-output terminal PAD is held at 0 V. Such characteristics are of a diode.
Next, path 2 in the semiconductor device shown in FIG. 3 from the external input-output terminal PAD to the ground terminal VSS will be described. When the potential of the power supply terminal VDD is increased in the positive direction with respect to the external input-output terminal PAD, the first thyristor SCR1 allows a large amount of current to flow therethrough due to a significantly small potential difference of about 0.7 V. Therefore, a major part of the potential difference is applied to the second thyristor SCR2. As a result, the current-voltage characteristics of the portion represented by path 2 are substantially the same as what is seen in the positive direction side of the graph of FIG. 2.
Thus, when the electrostatic discharge phenomenon occurs in which the potential of the power supply terminal VDD is increased in the positive direction where the external input-output terminal PAD is held at 0 V, a discharge current flows through path 1 or path 2 shown in FIG. 3.
A fundamental thyristor as shown in FIG. 1 fabricated by a CMOS process does not have a particular trigger structure. A turn-on voltage (a voltage from which a thyristor begins exhibiting a negative resistance) of such a fundamental thyristor is determined by a breakdown voltage of the low-concentration N-type semiconductor region 3 and the low-concentration P-type semiconductor region 4, and has a value of several tens of volts. There is a known thyristor having a trigger structure which can be fabricated without an additional process to a CMOS process, and in which the turn-on voltage can be lowered. An example of such a thyristor is shown in FIG. 7.
In the thyristor shown in FIG. 7, a low-concentration N-type semiconductor region 17 and a low-concentration P-type semiconductor region 18 are provided side by side in a horizontal direction on a P-type silicon substrate 15. High-concentration N-type semiconductor regions 19, 21, and a high-concentration P-type semiconductor region 22 are provided on the low-concentration N-type semiconductor region 17 and are isolated from one another by an isolation region 16. High-concentration N-type semiconductor region 20, and high-concentration P-type semiconductor regions 23 and 24 are provided on the low-concentration P-type semiconductor region 18, and are isolated from one another by the isolation region 16. The high-concentration P-type semiconductor region 24 penetrates from the low-concentration N-type semiconductor region 17 into the low-concentration P-type semiconductor region 18. A gate silicon 51 is provided on the low-concentration N-type semiconductor region 17 between the high-concentration P-type semiconductor region 24 and the high-concentration N-type semiconductor region 21 provided in the low-concentration N-type semiconductor region 17. An anode terminal T3 is connected to the high-concentration N-type semiconductor region 19 and the high-concentration P-type semiconductor region 22, and a cathode terminal T4 is connected to the high-concentration N-type semiconductor region 20 and the high-concentration P-type semiconductor region 23.
In such a thyristor, the high-concentration P-type semiconductor region 24 is provided at a junction portion between the low-concentration P-type semiconductor region 18 and the low-concentration N-type semiconductor region 17. Voltage endurance between the high-concentration P-type semiconductor region 24 and the low-concentration N-type semiconductor region 17 is lower than voltage endurance between the low-concentration P-type semiconductor region 18 and the low-concentration N-type semiconductor region 17. Therefore, the junction portion between the high-concentration P-type semiconductor region 24 and the low-concentration N-type semiconductor region 17 serves as a trigger. However, also in this thyristor, the turn-on voltage is about 10 to 20 V. It is difficult to reduce the turn-on voltage to lower than or equal to the breakdown voltage of the junction portion between the high-concentration P-type semiconductor region 24 and the low-concentration N-type semiconductor region 17.
Therefore, even when such a thyristor is used as a part of a static electricity protection circuit in the semiconductor device shown in FIG. 3, if an electrostatic discharge phenomenon occurs in which the potential of the power supply terminal VDD is increased in the positive direction where the potential of the external input-output terminal PAD is referenced as 0 V, most current actually flows through path 1 but not path 2 as shown in FIG. 3, so that current is concentrated into the P-type MOS transistor PMOS. As a result, the voltage endurance of the P-type MOS transistor PMOS against electrostatic discharge determines the voltage endurance of the whole circuit against electrostatic discharge.
In the P-type MOS transistor PMOS, there is a steep portion in the concentration gradient in a channel direction of the transistor. Therefore, discharge current tends to be locally concentrated and the endurance of the P-type MOS transistor PHOS against static electricity damage is likely to be reduced. Such a tendency of discharge current to be locally concentrated causes the source/drain diffused resistance and the gate conductor resistance of the P-type MOS transistor PMOS to be reduced. Therefore, if the P-type MOS transistor PMOS includes metal silicide provided on the high-concentration P-type semiconductor region, such a tendency is more significant. In this case, the endurance against static electricity damage is likely to be further reduced.
Japanese Laid-Open Publication No. 10-70238 discloses a static electricity protection circuit in which a first thyristor is provided between an input-output terminal and a ground terminal, and a second thyristor is provided between a power supply terminal and a ground terminal. Even in this static electricity protection circuit, when an ON voltage for switching a P-type MOS transistor ON is reduced, current is not discharged through path including the first and second thyristors, but discharge current is concentrated into the P-type MOS transistor. As a result, the voltage endurance against static electricity damage is likely to be reduced.
According to an aspect of the present invention, a protection circuit for protecting a semiconductor device from being damaged due to an excessively high applied voltage, includes a P-type MOS transistor provided between an external input-output terminal and a power supply line, an N-type MOS transistor provided between the P-type MOS transistor and a ground line, a first thyristor provided between the external input-output terminal and the ground line, an anode portion thereof being connected to the external input-output terminal side, and a cathode portion thereof being connected to the ground line, a second thyristor provided between the power supply line and the ground line, an anode portion thereof being connected to the power supply line, and a cathode portion thereof being connected to the ground line, and a resistance portion provided at a predetermined location of a conductor extending from a branch node between the P-type MOS transistor and the N-type MOS transistor to the power supply line via the P-type MOS transistor.
In one embodiment of this invention, the resistance value of the resistance portion is a value such that when a potential of a power supply terminal is increased in a positive direction with respect to the external input-output terminal, a first minimum value of a voltage causing a first path to be damaged, the first path ranging from the external input-output terminal to the power supply terminal via the P-type MOS transistor, the resistance portion, and the power supply line, is greater than a second minimum value of a voltage causing a second path to exhibit negative resistance, the second path ranging from the external input-output terminal to the power supply terminal via the first thyristor, the ground line, the second thyristor, and the power supply line.
In one embodiment of this invention, each of the first thyristor and the second thyristor has a trigger structure.
In one embodiment of this invention, a conductor including first and second conductor layers connected via a through hole, is connected to the P-type MOS transistor. The through hole forms the resistance portion.
In one embodiment of this invention, the resistance portion is formed of a high impurity concentration region provided in a low impurity concentration region provided on a semiconductor substrate. The conductivity type of the high impurity concentration region is opposite to the conductivity type of the low impurity concentration region.
In one embodiment of this invention, the resistance portion is formed of a low impurity concentration region provided in a semiconductor substrate.
In one embodiment of this invention, a pair of high impurity concentration regions are provided on the low impurity concentration region. The pair of high impurity concentration regions are separated by an isolation region; the conductivity type of the high impurity concentration regions is the same as that of the low impurity concentration region. A conductor is connected to each of the pair of high impurity concentration regions.
In one embodiment of this invention, the resistance portion is formed of a metal conductor ranging from the external input-output terminal to the power supply terminal via the P-type MOS transistor and the power supply line.
According to another aspect of the present invention, a semiconductor device including an external input-output terminal is provided, in which the protection circuit of the present invention is connected to the external input-output terminal.
In one embodiment of this invention, the semiconductor device further includes one or more external input-output terminals, in which a protection circuit of the present invention is connected to each external input-output terminal, and the resistance portion is formed of the resistance of the power supply line connected to each protection circuit.
Thus, the invention described herein makes possible the advantages of providing: a protection circuit including a thyristor for preventing static electricity damage in a semiconductor device fabricated by a CMOS process, such as a semiconductor integrated circuit, in which a discharge path including a thyristor is provided to avoid concentration of current into a P-type MOS transistor serving as an input-output portion, whereby static electricity damage of the semiconductor device is effectively prevented; a semiconductor device including the same; a protection circuit used in a semiconductor device fabricated by a CMOS process, in which static electricity damage of the semiconductor device is effectively prevented without performing any particular additional process step; and a semiconductor device including the same.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.